rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultrafast comparators ad96685/ad96687 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 ad96685 functional block diagram ad96687 functional block diagram features fast: 2.5 ns propagation delay low power: 118 mw per comparator packages: dip, to-100, soic, plcc power supplies: +5 v, C5.2 v logic compatibility: ecl mil-std-883 versions available 50 ps delay dispersion applications high speed triggers high speed line receivers threshold detectors window comparators peak detectors general description the ad96685 and ad96687 are ultrafast voltage comparators. the ad96685 is a single comparator with 2.5 ns propagation delay; the ad96687 is an equally fast dual comparator. both devices feature 50 ps propagation delay dispersion which is a particularly important characteristic of high speed comparators. it is a measure of the difference in propagation delay under dif- fering overdrive conditions. a fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the common- mode range from C2.5 v to +5 v. outputs are complementary digital signals fully compatible with ecl 10 k and 10 kh logic families. the outputs provide sufficient drive current to directly drive transmission lines terminated in 50 w to C2 v. a level sen- sitive latch input is included which permits tracking, track-hold, or sample-hold modes of operation. the ad96685 and ad96687 are available in both industrial, C25 c to +85 c, and military temperature ranges. industrial range devices are available in 16-pin dip, soic, and 20-lead plcc; additionally, the ad96685 is available in a 10-pin, to-100 metal can.
rev. c C2C ad96685/ad96687Cspecifications electrical characteristics (positive supply voltage = +5.0 v; negative supply voltage = C5.2 v, unless otherwise noted) industrial temp. range C25 8 c to +85 8 c military temp. range C55 8 c to +125 8 c test AD96685BH/bq/bp/br ad96687bq/bp/br ad96685tq ad96687tq parameter temp level min typ max min typ max min typ max min typ max units input characteristics input offset voltage 4 +25 ci 1 2 12 12 12 mv full vi 3333mv input offset drift full v 20 20 20 20 m v/ c input bias current +25 ci 710710710710 m a full vi 13 13 16 16 m a input offset current +25 c i 0.1 1.0 0.1 1.0 0.1 1.0 0.1 1.0 m a full vi 1.2 1.2 1.2 1.2 m a input resistance +25 c v 200 200 200 200 k w input capacitance +25 cv2 222pf input voltage ranges full vi C2.5 +5.0 C2.5 +5.0 C2.5 +5.0 C2.5 +5.0 v common-mode rejection ratio full vi 80 90 80 90 80 90 80 90 db enable input logic 1 voltage full vi C1.1 C1.1 C1.1 C1.1 v logic 0 voltage full vi C1.5 C1.5 C1.5 C1.5 v logic 1 current full vi 40 40 40 40 m a logic 0 current full vi 5555 m a digital outputs 6 logic 1 voltage full vi C1.1 C1.1 C1.1 C1.1 v logic 0 voltage full vi C1.5 C1.5 C1.5 C1.5 v switching performances propagation delays 7 input to output high +25 c iv 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 ns input to output low +25 c iv 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 ns latch enable to output high +25 c iv 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 ns latch enable to output low +25 c iv 2.5 3.5 2.5 3.5 2.5 3.5 2.5 3.5 ns dispersions 8 +25 c v 50 50 50 50 ps latch enable minimum pulse width +25 c iv 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 ns minimum setup time +25 c iv 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns minimum hold time +25 c iv 0.5 1.0 0.5 1.0 0.5 1.0 0.5 1.0 ns power supply 9 positive supply current (+5.0 v) full vi 8 9 15 18 8 9 15 18 ma negative supply current (C5.2 v) full vi 15 18 31 36 15 18 31 36 ma power supply rejection ratio 10 full vi 60 70 60 70 60 70 60 70 db notes 1 absolute maximum ratings are limiting values, may be applied individually, and beyond which serviceability of the circuit may be impaired. functional operation under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 under no circumstances should the input voltages exceed the supply voltages . 3 typical thermal impedances . . . ad96685 metal can q ja = 172 c/w; q jc = 52 c/w ad96685 ceramic q ja = 115 c/w; q jc = 57 c/w ad96685 soic q ja = 170 c/w; q jc = 60 c/w ad96685 plcc q ja = 88 c/w; q jc = 45 c/w ad96687 ceramic q ja = 115 c/w; q jc = 57 c/w ad96687 soic q ja = 92 c/w; q jc = 47 c/w ad96687 plcc q ja = 81 c/w; q jc = 45 c/w absolute maximum ratings 1 positive supply voltage (+v s ) . . . . . . . . . . . . . . . . . . . . +6.5 v negative supply voltage (Cv s ) . . . . . . . . . . . . . . . . . . . C6.5 v input voltage range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v latch enable voltage . . . . . . . . . . . . . . . . . . . . . . . . Cv s to 0 v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ma operating temperature range 3 ad96685/87/bh/bq/bp/br . . . . . . . . . . . . C25 c to +85 c ad96685/87/tq . . . . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . . C55 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 c lead soldering temperature (10 sec) . . . . . . . . . . . . . +300 c explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c; 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature ex- tremes for commercial/industrial devices. 4 r s = 100 w . 5 input voltage range can be extended to C3.3 v if Cv s = C6.0 v. 6 outputs terminated through 50 w to C2.0 v. 7 propagation delays measured with 100 mv pulse (10 mv overdrive), to 50% transition point of the output. 8 change in propagation delay from 100 mv to 1 v input overdrive. 9 supply voltages should remain stable within 5% for normal operation. 10 measured at 5% of +v s and Cv s . specifications subject to change without notice.
ad96685/ad96687 C3C rev. c functional description pin name description +v s positive supply terminal, nominally +5.0 v. noninverting input noninverting analog input of the differential input stage. the noninverting input must be driven in conjunction with the inverting input. inverting input inverting analog input of the differential input stage. the inverting input must be driven in conjunction with the noninverting input. latch enable in the compare mode (logic high), the output will track changes at the input of the compara- tor. in the latch mode (logic low), the output will reflect the input state just prior to the comparator being placed in the latch mode. latch enable must be driven in conjunction with latch enable for the ad96687. latch enable in the compare mode (logic low), the output will track changes at the input of the comparator. in the latch mode (logic high), the output will reflect the input state just prior to the compara- tor being placed in the latch mode. latch enable must be driven in conjunction with latch enable for the ad96687. Cv s negative supply terminal, nominally C5.2 v. q one of two complementary outputs. q will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (pro- vided the comparator is in the compare mode). see latch enable and latch enable (ad96687 only) for additional information. q one of two complementary outputs. q will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). see latch enable and latch en- able (ad96687 only) for additional information. ground 1 one of two grounds, but primarily associated with the digital ground. both grounds should be con- nected together near the comparator. ground 2 one of two grounds, but primarily associated with the analog ground. both grounds should be con- nected together near the comparator. pin designations ad96685bq/tq/br ad96687bq/tq/br ad96685bp AD96685BH ad96687bp nc = no connect nc = no connect nc = no connect
ad96685/ad96687 C4C rev. c system timing diagram t s C minimum setup time t h C minimum hold time t pd C input to output delay t pd (e) C latch enable to output delay t pw (e) C minimum latch enable pulse width v os C input offset voltage v od C overdrive voltage die layout and mechanical information die dimensions (ad96687) . . . . . . . . 77 3 60 3 15 ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride die attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold eutectic bond wire . . . . . . . . 1.25 mil, aluminum; ultrasonic bonding or 1 mil, gold, gold ball bonding die dimensions (ad96685) . . . . . . . . 44 3 50 3 15 ( 2) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride die attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold eutectic bond wire . . . . . . . . 1.25 mil, aluminum; ultrasonic bonding or 1 mil, gold, gold ball bonding
ad96685/ad96687 C5C rev. c applications information the ad96685/87 comparators are very high speed devices. consequently, high speed design techniques must be employed to achieve the best performance. the most critical aspect of any ad96685/87 design is the use of a low impedance ground plane. another area of particular importance is power supply decoupling. normally, both power supply connections should be separately decoupled to ground through 0.1 m f ceramic and 0.001 m f mica capacitors. the basic design of comparator cir- cuits makes the negative supply somewhat more sensitive to variations. as a result more attention should be placed on insur- ing a clean negative supply. the latch enable input is active low (latched). if the latching function is not used, the latch enable input should be grounded (ground is an ecl logic high). the latch enable input of the ad96687 should be tied to C2.0 v or left floating, to disable the latching function. an alternate use of the latch enable input is as a hysteresis control input. by varying the voltage at the latch enable input for the ad96685 and the differential voltage between both latch inputs for the ad96687, small variations in the hysteresis can be achieved. occasionally, one of the two comparator stages within the ad96687 will not be used. the inputs of the unused compara- tor should not be allowed to float. the high internal gain may cause the output to oscillate (possibly affecting the other com- parator which is being used) unless the output is forced into a fixed state. this is easily accomplished by insuring that the two inputs are at least one diode drop apart, while also grounding the latch enable input. the best performance will be achieved with the use of proper ecl terminations. the open-emitter outputs of the ad96685/87 are designed to be terminated through 50 w resis- tors to C2.0 v, or any other equivalent ecl termination. if high speed ecl signals must be routed more than a few centimeters, microstrip or stripline techniques may be required to insure proper transition times and prevent output ringing. the ad96685/87 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mv to 1 v. propagation delay dispersion is the change in propagation delay which results from a change in the degree of overdrive (how far the switching point is exceeded by the input). the overall result is a higher degree of timing accuracy since the ad96685/87 is far less sensitive to input variations than most comparator designs. typical applications high speed sampling circuit high speed window comparator ordering guide temperature package model type range description options AD96685BH single C25 c to +85 c 10-pin can, industrial h-10a ad96685bp single C25 c to +85 c 20-pin plcc, industrial p-20a ad96685bq single C25 c to +85 c 16-pin dip, industrial q-16 ad96685br single C25 c to +85 c 16-pin soic, industrial r-16a ad96685bp-reel single C25 c to +85 c 20-pin plcc, industrial p-20a ad96685tq single C55 c to +125 c 16-pin dip, extended temperature q-16 ad96687bp dual C25 c to +85 c 20-pin plcc, industrial p-20a ad96687bq dual C25 c to +85 c 16-pin dip, industrial q-16 ad96687br dual C25 c to +85 c 16-pin soic, industrial r-16a ad96687br-reel dual C25 c to +85 c 16-pin soic, industrial r-16a ad96687tq dual C55 c to +125 c 16-pin dip, extended temperature q-16
ad96685/ad96687 C6C rev. c outline dimensions dimensions shown in inches and (mm). c1096bC2C9/96 printed in u.s.a. 16-pin ceramic dip 20-pin lcc 16-pin soic 20-pin plcc 10-pin to-100 metal can
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